1. Field of the Invention
The present invention relates to electrical signal processing, and, in particular, to the synchronization of timing between parallel signal processing circuits.
2. Description of the Related Art
Data skew refers to differences in timing between different channels that operate in parallel in signal processing circuitry. Although ideally data should be presented at the outputs of the parallel processing channels at the same time (i.e., synchronously), these timing differences can result in output data being presented at different times (i.e., asynchronously). Data skew is an undesirable characteristic of parallel processing circuits that are intended to be used to perform identical—or at least similar—synchronous processing on different sets of input data.
One way to reduce the effects of data skew is to implement each channel with elastic storage devices to enable buffering of data in any channel as needed to adjust for data skew between different channels. In many signal processing applications, especially those involving high-speed signal processing (e.g., at processing speeds in the GHz range or higher), achieving more than a few nanoseconds of elastic data storage can be prohibitively expensive.